?屬性????????????大小?????日期????時間???名稱
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?????文件????????247??2007-02-14?14:30??veriloga_example\biterrorrate.sp

?????文件????????558??2007-02-14?14:30??veriloga_example\biterrorrate.va

?????文件????????783??2007-02-14?14:30??veriloga_example\bjt.sp

?????文件??????13859??2007-02-14?14:30??veriloga_example\bjt.va

?????文件????????654??2007-02-14?14:30??veriloga_example\colpitts.sp

?????文件????????431??2007-02-14?14:30??veriloga_example\dac.sp

?????文件???????1772??2007-02-14?14:30??veriloga_example\dac.va

?????文件????????172??2007-02-14?14:30??veriloga_example\deadband.sp

?????文件????????481??2007-02-14?14:30??veriloga_example\deadband.va

?????文件????????505??2007-02-14?14:30??veriloga_example\ecl.sp

?????文件????????231??2007-02-14?14:30??veriloga_example\opamp.sp

?????文件???????2382??2007-02-14?14:30??veriloga_example\opamp.va

?????文件????????148??2007-02-14?14:30??veriloga_example\pll.sp

?????文件???????1807??2007-02-14?14:30??veriloga_example\pll.va

?????文件????????611??2007-02-14?14:30??veriloga_example\psfet.sp

?????文件??????14467??2007-02-14?14:30??veriloga_example\psfet.va

?????文件????????126??2007-02-14?14:30??veriloga_example\resistor.sp

?????文件????????158??2007-02-14?14:30??veriloga_example\resistor.va

?????文件????????303??2007-02-14?14:30??veriloga_example\sample_hold.sp

?????文件????????432??2007-02-14?14:30??veriloga_example\sample_hold.va

?????文件????????132??2007-02-14?14:30??veriloga_example\sinev.sp

?????文件????????417??2007-02-14?14:30??veriloga_example\sinev.va

?????目錄??????????0??2012-04-12?21:57??veriloga_example

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????????????????40676????????????????????23