資源簡介
流片驗證過的wishbone接口的 I2C總線 verilog 代碼
代碼片段和文件信息
?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????文件??????11425??2009-03-11?00:36??trunk\bench\verilog\i2c_slave_model.v
?????文件???????3840??2009-03-11?00:36??trunk\bench\verilog\spi_slave_model.v
?????文件??????14491??2009-03-11?00:36??trunk\bench\verilog\tst_bench_top.v
?????文件???????5566??2009-03-11?00:36??trunk\bench\verilog\wb_master_model.v
?????目錄??????????0??2002-01-31?03:05??trunk\bench\verilog
?????目錄??????????0??2002-01-31?03:05??trunk\bench
?????文件?????211471??2009-03-11?00:36??trunk\doc\i2c_specs.pdf
?????文件?????464896??2009-03-11?00:36??trunk\doc\src\I2C_specs.doc
????..A..H.???????162??2009-06-24?09:31??trunk\doc\src\~$C_specs.doc
?????目錄??????????0??2002-01-31?03:05??trunk\doc\src
?????目錄??????????0??2002-01-31?03:05??trunk\doc
?????文件??????18342??2009-03-11?00:36??trunk\rtl\verilog\i2c_master_bit_ctrl.v
?????文件??????10547??2009-03-11?00:36??trunk\rtl\verilog\i2c_master_byte_ctrl.v
?????文件???????3011??2009-03-11?00:36??trunk\rtl\verilog\i2c_master_defines.v
?????文件??????10114??2009-03-11?00:36??trunk\rtl\verilog\i2c_master_top.v
?????文件?????????23??2009-03-11?00:36??trunk\rtl\verilog\timescale.v
?????目錄??????????0??2002-01-31?03:05??trunk\rtl\verilog
?????文件??????13542??2009-03-11?00:36??trunk\rtl\vhdl\I2C.VHD
?????文件??????19261??2009-03-11?00:36??trunk\rtl\vhdl\i2c_master_bit_ctrl.vhd
?????文件??????12630??2009-03-11?00:36??trunk\rtl\vhdl\i2c_master_byte_ctrl.vhd
?????文件??????13452??2009-03-11?00:36??trunk\rtl\vhdl\i2c_master_top.vhd
?????文件????????789??2009-03-11?00:36??trunk\rtl\vhdl\readme
?????文件???????6959??2009-03-11?00:36??trunk\rtl\vhdl\tst_ds1621.vhd
?????目錄??????????0??2002-01-31?03:05??trunk\rtl\vhdl
?????目錄??????????0??2002-01-31?03:05??trunk\rtl
?????文件??????????5??2009-03-11?00:36??trunk\sim\i2c_verilog\run\ncverilog.key
?????文件???????4697??2009-03-11?00:36??trunk\sim\i2c_verilog\run\ncverilog.log
?????文件????????514??2009-03-11?00:36??trunk\sim\i2c_verilog\run\run
?????目錄??????????0??2002-01-07?10:51??trunk\sim\i2c_verilog\run
?????目錄??????????0??2002-01-31?03:05??trunk\sim\i2c_verilog
............此處省略8個文件信息
-----------?---------??----------?-----??----
?????文件??????11425??2009-03-11?00:36??trunk\bench\verilog\i2c_slave_model.v
?????文件???????3840??2009-03-11?00:36??trunk\bench\verilog\spi_slave_model.v
?????文件??????14491??2009-03-11?00:36??trunk\bench\verilog\tst_bench_top.v
?????文件???????5566??2009-03-11?00:36??trunk\bench\verilog\wb_master_model.v
?????目錄??????????0??2002-01-31?03:05??trunk\bench\verilog
?????目錄??????????0??2002-01-31?03:05??trunk\bench
?????文件?????211471??2009-03-11?00:36??trunk\doc\i2c_specs.pdf
?????文件?????464896??2009-03-11?00:36??trunk\doc\src\I2C_specs.doc
????..A..H.???????162??2009-06-24?09:31??trunk\doc\src\~$C_specs.doc
?????目錄??????????0??2002-01-31?03:05??trunk\doc\src
?????目錄??????????0??2002-01-31?03:05??trunk\doc
?????文件??????18342??2009-03-11?00:36??trunk\rtl\verilog\i2c_master_bit_ctrl.v
?????文件??????10547??2009-03-11?00:36??trunk\rtl\verilog\i2c_master_byte_ctrl.v
?????文件???????3011??2009-03-11?00:36??trunk\rtl\verilog\i2c_master_defines.v
?????文件??????10114??2009-03-11?00:36??trunk\rtl\verilog\i2c_master_top.v
?????文件?????????23??2009-03-11?00:36??trunk\rtl\verilog\timescale.v
?????目錄??????????0??2002-01-31?03:05??trunk\rtl\verilog
?????文件??????13542??2009-03-11?00:36??trunk\rtl\vhdl\I2C.VHD
?????文件??????19261??2009-03-11?00:36??trunk\rtl\vhdl\i2c_master_bit_ctrl.vhd
?????文件??????12630??2009-03-11?00:36??trunk\rtl\vhdl\i2c_master_byte_ctrl.vhd
?????文件??????13452??2009-03-11?00:36??trunk\rtl\vhdl\i2c_master_top.vhd
?????文件????????789??2009-03-11?00:36??trunk\rtl\vhdl\readme
?????文件???????6959??2009-03-11?00:36??trunk\rtl\vhdl\tst_ds1621.vhd
?????目錄??????????0??2002-01-31?03:05??trunk\rtl\vhdl
?????目錄??????????0??2002-01-31?03:05??trunk\rtl
?????文件??????????5??2009-03-11?00:36??trunk\sim\i2c_verilog\run\ncverilog.key
?????文件???????4697??2009-03-11?00:36??trunk\sim\i2c_verilog\run\ncverilog.log
?????文件????????514??2009-03-11?00:36??trunk\sim\i2c_verilog\run\run
?????目錄??????????0??2002-01-07?10:51??trunk\sim\i2c_verilog\run
?????目錄??????????0??2002-01-31?03:05??trunk\sim\i2c_verilog
............此處省略8個文件信息
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