91av视频/亚洲h视频/操亚洲美女/外国一级黄色毛片 - 国产三级三级三级三级

  • 大小: 25KB
    文件類型: .zip
    金幣: 2
    下載: 0 次
    發布日期: 2021-06-06
  • 語言: 其他
  • 標簽: verilog??sublime??

資源簡介

sublime text3 下 高效開發verilog的插件合集 相關應用介紹在博文
https://editor.csdn.net/md?articleId=104506830

資源截圖

代碼片段和文件信息

import?sublime
import?sublime_plugin
import?re
import?os
import?time
from?os.path?import?normpath?dirname

sublime_version?=?2
if?int(sublime.version())?>?3000:
????sublime_version?=?3


def?find_tags_relative_to(file_name):
????if?not?file_name:
????????return?None

????dirs?=?dirname(normpath(file_name)).split(os.path.sep)

????while?dirs:
????????joined?=?os.path.sep.join(dirs?+?[‘.tags‘])
????????if?os.path.exists(joined)?and?not?os.path.isdir(joined):
????????????return?joined
????????else:
????????????dirs.pop()

????return?None


def?get_match(pattern?string?group_number):
????compiled_pattern?=?re.compile(pattern)
????match?=?re.search(compiled_pattern?string)
????return?match.group(group_number)


def?get_list(text_command?pattern?group_number?split_flag):
????match_list?=?[]
????regions?=?text_command.view.find_all(pattern)
????for?region?in?regions:
????????if?‘comment‘?in?text_command.view.scope_name(region.begin()):
????????????continue
????????line_string?=?text_command.view.substr(region)
????????match_substring?=?get_match(pattern?line_string?group_number)
????????if?split_flag:
????????????port_list?=?match_substring.split(‘‘)
????????????for?each_port?in?port_list:
????????????????match_list.append(each_port.strip())
????????else:
????????????if?match_substring?is?not?None:
????????????????match_list.append(match_substring.strip())
????????????else:
????????????????match_list.append(match_substring)
????return?match_list


def?find_insert_region(text_command?insert_pattern?insert_mark?search_start):
????insert_region?=?text_command.view.find(insert_pattern?search_start)
????if?(insert_region?is?None?and?sublime_version?==?2)?or?(insert_region.begin()?==?-1?and?sublime_version?==?3):
????????sublime.status_message(‘Can?not?find?the?“‘?+?insert_mark?+?‘“?mark?!‘)
????????raise?Exception(‘Can?not?find?the?“‘?+?insert_mark?+?‘“?mark?!‘)
????return?insert_region


def?check_file_ext(file_name):
????ext_name?=?os.path.splitext(file_name)[1]
????if?ext_name?!=?‘.v‘?and?ext_name?!=?‘.V‘:
????????sublime.status_message(
????????????‘This?file?“‘?+?file_name?+?‘“?is?not?a?verilog?file?!‘)
????????raise?Exception(
????????????‘This?file?“‘?+?file_name?+?‘“?is?not?a?verilog?file?!‘)


class?AutoDefCommand(sublime_plugin.TextCommand):

????“““auto?add?wire?declaration?for?instances?to?connect“““

????def?run(self?edit):
????????file_name?=?self.view.file_name()
????????check_file_ext(file_name)
????????undefined_instance_port_dict?=?{}
????????insert_pattern?=?r“/\*\bautodef\b\*/“
????????insert_mark?=?“/*autodef*/“
????????insert_region?=?find_insert_region(
????????????self?insert_pattern?insert_mark?0)
????????insert_point?=?insert_region.end()
????????search_defined_pattern?=?r‘^\s*(?:\b(?:input|wire|reg|signed)\b)\s*(?:\[\S+\s*:\s*\S+\])*\s*((\w+\s*[]*\s*)*)‘
????????search_instance_pattern?=?r‘^\s*(?:[.]\w+\s*\(\s*)(\w+)\s*(\[\s*\w+\s*[:]\s*\w+\s*\])*\)‘
????????instance_port_name_list?=?get_list(self?search_instanc

?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????文件??????????85??2020-02-25?22:16??readme.txt
?????目錄???????????0??2018-11-19?18:32??Sublime-Text-Snippets-for-Verilog-master\
?????文件?????????163??2018-10-18?13:55??Sublime-Text-Snippets-for-Verilog-master\always?combination.sublime-snippet
?????文件?????????226??2018-10-18?13:55??Sublime-Text-Snippets-for-Verilog-master\always?sequential.sublime-snippet
?????文件?????????244??2018-11-19?18:07??Sublime-Text-Snippets-for-Verilog-master\case?switch.sublime-snippet
?????文件?????????148??2013-11-06?01:50??Sublime-Text-Snippets-for-Verilog-master\conditional.sublime-snippet
?????文件?????????207??2013-11-06?01:50??Sublime-Text-Snippets-for-Verilog-master\elif.sublime-snippet
?????文件?????????136??2018-11-19?18:57??Sublime-Text-Snippets-for-Verilog-master\else.sublime-snippet
?????文件?????????243??2013-11-06?01:50??Sublime-Text-Snippets-for-Verilog-master\for?cicle.sublime-snippet
?????文件????????1482??2013-11-06?01:50??Sublime-Text-Snippets-for-Verilog-master\FSM.Sublime-snippet
?????文件?????????923??2018-11-19?17:53??Sublime-Text-Snippets-for-Verilog-master\Head?notes.sublime-snippet
?????文件?????????146??2018-11-10?19:44??Sublime-Text-Snippets-for-Verilog-master\if.sublime-snippet
?????文件?????????151??2018-11-19?18:04??Sublime-Text-Snippets-for-Verilog-master\inout?bit.sublime-snippet
?????文件?????????149??2018-10-18?13:28??Sublime-Text-Snippets-for-Verilog-master\inout.sublime-snippet
?????文件?????????151??2018-11-19?18:03??Sublime-Text-Snippets-for-Verilog-master\input?bit.sublime-snippet
?????文件?????????144??2018-11-19?18:05??Sublime-Text-Snippets-for-Verilog-master\input.sublime-snippet
?????文件?????????150??2013-11-06?01:50??Sublime-Text-Snippets-for-Verilog-master\integer.sublime-snippet
?????文件?????????377??2018-11-19?18:32??Sublime-Text-Snippets-for-Verilog-master\Main?code?note.sublime-snippet
?????文件?????????230??2018-11-19?18:03??Sublime-Text-Snippets-for-Verilog-master\module?.sublime-snippet
?????文件?????????152??2018-11-19?18:06??Sublime-Text-Snippets-for-Verilog-master\output?bit.sublime-snippet
?????文件?????????145??2018-11-19?18:05??Sublime-Text-Snippets-for-Verilog-master\output.sublime-snippet
?????文件?????????351??2018-10-18?13:44??Sublime-Text-Snippets-for-Verilog-master\Param?notes.sublime-snippet
?????文件?????????152??2018-11-19?18:08??Sublime-Text-Snippets-for-Verilog-master\parameter.sublime-snippet
?????文件?????????136??2013-11-06?01:50??Sublime-Text-Snippets-for-Verilog-master\README.md
?????文件?????????150??2018-10-18?13:40??Sublime-Text-Snippets-for-Verilog-master\register?array.sublime-snippet
?????文件?????????142??2018-11-19?18:33??Sublime-Text-Snippets-for-Verilog-master\register.sublime-snippet
?????文件?????????154??2018-10-18?13:39??Sublime-Text-Snippets-for-Verilog-master\wire?array.sublime-snippet
?????文件?????????147??2018-10-18?13:38??Sublime-Text-Snippets-for-Verilog-master\wire.sublime-snippet
?????目錄???????????0??2018-11-10?19:40??sublimetext-Verilog-master\
?????文件?????????582??2011-09-29?13:13??sublimetext-Verilog-master\Comments?(ucfconstraints).tmPreferences
?????文件?????????964??2011-09-29?13:13??sublimetext-Verilog-master\Comments?(verilog).tmPreferences
............此處省略15個文件信息

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