?屬性????????????大小?????日期????時(shí)間???名稱
-----------?---------??----------?-----??----
?????目錄???????????0??2014-07-09?18:56??16\
?????文件???????12673??2011-07-14?01:00??16\IrDA.bdf
?????文件???????16727??2011-07-14?00:28??16\IrDA_TOP.bdf
?????文件????????1276??2011-07-14?00:02??16\IrDAnios.bsf
?????文件????????2987??2011-07-14?00:09??16\PLL.bsf
?????目錄???????????0??2014-07-09?18:56??16\Verilog?HDL?Files\
?????文件????????2438??2011-07-13?23:53??16\Verilog?HDL?Files\IrDA_DATABus.v
?????文件??????208607??2011-07-14?00:02??16\Verilog?HDL?Files\IrDAnios.v
?????文件?????????296??2011-07-14?00:02??16\Verilog?HDL?Files\IrDAnios_inst.v
?????文件???????14572??2011-07-14?00:09??16\Verilog?HDL?Files\PLL.v
?????文件????????2102??2011-07-14?00:02??16\Verilog?HDL?Files\RW_Ctr.v
?????文件????????1815??2011-07-14?00:02??16\Verilog?HDL?Files\Status.v
?????文件????????1534??2011-07-14?00:53??16\Verilog?HDL?Files\UART.V
?????文件????????1942??2011-07-13?22:37??16\Verilog?HDL?Files\Uart_tb.v
?????文件??????292744??2011-07-14?00:02??16\Verilog?HDL?Files\cpu_0.v
?????文件????????6774??2011-07-14?00:02??16\Verilog?HDL?Files\cpu_0_jtag_debug_module_sysclk.v
?????文件????????7997??2011-07-14?00:02??16\Verilog?HDL?Files\cpu_0_jtag_debug_module_tck.v
?????文件????????9440??2011-07-14?00:02??16\Verilog?HDL?Files\cpu_0_jtag_debug_module_wrapper.v
?????文件????????6121??2011-07-14?00:02??16\Verilog?HDL?Files\cpu_0_mult_cell.v
?????文件????????1342??2011-07-14?00:02??16\Verilog?HDL?Files\cpu_0_oci_test_bench.v
?????文件???????28436??2011-07-14?00:02??16\Verilog?HDL?Files\cpu_0_test_bench.v
?????文件???????18226??2011-07-14?00:02??16\Verilog?HDL?Files\epcs_flash_controller_0.v
?????文件????????1214??2011-07-13?20:40??16\Verilog?HDL?Files\irda_uart.v
?????文件????????2175??2011-07-13?20:09??16\Verilog?HDL?Files\irda_uart_tb.v
?????文件????????3041??2011-07-13?20:31??16\Verilog?HDL?Files\irendec.v
?????文件???????22689??2011-07-14?00:02??16\Verilog?HDL?Files\jtag_uart_0.v
?????文件????????3764??2011-07-14?00:02??16\Verilog?HDL?Files\onchip_memory2_0.v
?????文件????????4485??2011-07-13?23:00??16\Verilog?HDL?Files\receiver.v
?????文件????????4506??2004-12-13?09:23??16\Verilog?HDL?Files\reset_counter.v
?????文件????????3467??2011-07-13?22:57??16\Verilog?HDL?Files\transmit.v
?????文件????????8542??2004-12-13?09:23??16\delay_reset_block.bdf
............此處省略5個(gè)文件信息