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使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù),作為FPGA和DSP接口使用

代碼片段和文件信息
?屬性????????????大小?????日期????時間???名稱
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?????文件????????161??2009-07-24?10:25??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\?my_first_fpga\db\my_first_fpga_top.eco.cdb
?????文件????????154??2009-07-24?10:25??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\?my_first_fpga\db\my_first_fpga_top.sld_design_entry.sci
?????文件????????917??2009-07-24?10:25??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\?my_first_fpga\my_first_fpga.qpf
?????文件?????????90??2009-07-24?10:25??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\?my_first_fpga\my_first_fpga.qws
?????文件???????3031??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\add_sub_gub.tdf
?????文件??????37694??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\altsyncram_9pf1.tdf
?????文件???????2090??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\alt_synch_pipe_oc8.tdf
?????文件???????2095??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\alt_synch_pipe_pc8.tdf
?????文件???????5121??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\a_fefifo_ctc.tdf
?????文件???????3360??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\a_fefifo_htc.tdf
?????文件???????1641??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\a_gray2bin_q4b.tdf
?????文件???????4415??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\a_graycounter_u06.tdf
?????文件???????4481??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\cntr_cta.tdf
?????文件???????7189??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dcfifo_mmc1.tdf
?????文件???????1571??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dffpipe_gd9.tdf
?????文件???????1882??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dffpipe_id9.tdf
?????文件???????1903??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dffpipe_jd9.tdf
?????文件???????2320??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dpram_jvr.tdf
?????文件???????2805??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(0).cnf.cdb
?????文件???????1353??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(0).cnf.hdb
?????文件???????6085??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(1).cnf.cdb
?????文件???????1478??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(1).cnf.hdb
?????文件???????2770??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(2).cnf.cdb
?????文件????????863??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(2).cnf.hdb
?????文件??????17940??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(3).cnf.cdb
?????文件???????3259??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(3).cnf.hdb
?????文件??????12120??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(4).cnf.cdb
?????文件???????1930??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(4).cnf.hdb
?????文件???????1853??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.asm.qmsg
?????文件?????????93??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.cbx.xml
............此處省略93個文件信息
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?????文件????????161??2009-07-24?10:25??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\?my_first_fpga\db\my_first_fpga_top.eco.cdb
?????文件????????154??2009-07-24?10:25??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\?my_first_fpga\db\my_first_fpga_top.sld_design_entry.sci
?????文件????????917??2009-07-24?10:25??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\?my_first_fpga\my_first_fpga.qpf
?????文件?????????90??2009-07-24?10:25??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\?my_first_fpga\my_first_fpga.qws
?????文件???????3031??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\add_sub_gub.tdf
?????文件??????37694??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\altsyncram_9pf1.tdf
?????文件???????2090??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\alt_synch_pipe_oc8.tdf
?????文件???????2095??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\alt_synch_pipe_pc8.tdf
?????文件???????5121??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\a_fefifo_ctc.tdf
?????文件???????3360??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\a_fefifo_htc.tdf
?????文件???????1641??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\a_gray2bin_q4b.tdf
?????文件???????4415??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\a_graycounter_u06.tdf
?????文件???????4481??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\cntr_cta.tdf
?????文件???????7189??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dcfifo_mmc1.tdf
?????文件???????1571??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dffpipe_gd9.tdf
?????文件???????1882??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dffpipe_id9.tdf
?????文件???????1903??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dffpipe_jd9.tdf
?????文件???????2320??2009-07-25?12:26??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\dpram_jvr.tdf
?????文件???????2805??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(0).cnf.cdb
?????文件???????1353??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(0).cnf.hdb
?????文件???????6085??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(1).cnf.cdb
?????文件???????1478??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(1).cnf.hdb
?????文件???????2770??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(2).cnf.cdb
?????文件????????863??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(2).cnf.hdb
?????文件??????17940??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(3).cnf.cdb
?????文件???????3259??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(3).cnf.hdb
?????文件??????12120??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(4).cnf.cdb
?????文件???????1930??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.(4).cnf.hdb
?????文件???????1853??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.asm.qmsg
?????文件?????????93??2010-02-27?11:08??使用verilog以及VHDL編寫的將串口數(shù)據(jù)轉(zhuǎn)換為32位并口數(shù)據(jù)\serial?ports2\db\serialports.cbx.xm
............此處省略93個文件信息
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