資源簡介
FPGA的設計實例合集,包括Verilog和VHDL,另外還包括一些文檔資料,主要是一些原理結構和編碼風格之類的,很實用.
代碼片段和文件信息
//?cube.cpp?:?Defines?the?class?behaviors?for?the?application.
//
//?This?is?a?part?of?the?Microsoft?Foundation?Classes?C++?library.
//?Copyright?(C)?1992-1998?Microsoft?Corporation
//?All?rights?reserved.
//
//?This?source?code?is?only?intended?as?a?supplement?to?the
//?Microsoft?Foundation?Classes?Reference?and?related
//?electronic?documentation?provided?with?the?library.
//?See?these?sources?for?detailed?information?regarding?the
//?Microsoft?Foundation?Classes?product.
#include?“stdafx.h“
#include?“cube.h“
#include?“mainfrm.h“
#include?“cubedoc.h“
#include?“cubeview.h“
#ifdef?_DEBUG
#undef?THIS_FILE
static?char?baseD_CODE?THIS_FILE[]?=?__FILE__;
#endif
/////////////////////////////////////////////////////////////////////////////
//?CCubeApp
BEGIN_MESSAGE_MAP(CCubeApp?CWinApp)
//{{AFX_MSG_MAP(CCubeApp)
ON_COMMAND(ID_APP_ABOUT?OnAppAbout)
//?NOTE?-?the?ClassWizard?will?add?and?remove?mapping?macros?here.
//????DO?NOT?EDIT?what?you?see?in?these?blocks?of?generated?code!
//}}AFX_MSG_MAP
//?Standard?file?based?document?commands
ON_COMMAND(ID_FILE_NEW?CWinApp::OnFileNew)
ON_COMMAND(ID_FILE_OPEN?CWinApp::OnFileOpen)
END_MESSAGE_MAP()
/////////////////////////////////////////////////////////////////////////////
//?CCubeApp?construction
CCubeApp::CCubeApp()
{
//?TODO:?add?construction?code?here
//?Place?all?significant?initialization?in?InitInstance
}
/////////////////////////////////////////////////////////////////////////////
//?The?one?and?only?CCubeApp?object
CCubeApp?theApp;
/////////////////////////////////////////////////////////////////////////////
//?CCubeApp?initialization
BOOL?CCubeApp::InitInstance()
{
//?Standard?initialization
//?If?you?are?not?using?these?features?and?wish?to?reduce?the?size
//??of?your?final?executable?you?should?remove?from?the?following
//??the?specific?initialization?routines?you?do?not?need.
Enable3dControls();
LoadStdProfileSettings();??//?Load?standard?INI?file?options?(including?MRU)
//?Register?the?application‘s?document?templates.??Document?templates
//??serve?as?the?connection?between?documents?frame?windows?and?views.
CSingleDocTemplate*?pDocTemplate;
pDocTemplate?=?new?CSingleDocTemplate(
IDR_MAINframe
RUNTIME_CLASS(CCubeDoc)
RUNTIME_CLASS(CMainframe)???????//?main?SDI?frame?window
RUNTIME_CLASS(CCubeView));
AddDocTemplate(pDocTemplate);
//?create?a?new?(empty)?document
OnFileNew();
if?(m_lpCmdLine[0]?!=?‘\0‘)
{
//?TODO:?add?command?line?processing?here
}
return?TRUE;
}
/////////////////////////////////////////////////////////////////////////////
//?CAboutDlg?dialog?used?for?App?About
class?CAboutDlg?:?public?CDialog
{
public:
CAboutDlg();
//?Dialog?Data
//{{AFX_DATA(CAboutDlg)
enum?{?IDD?=?IDD_ABOUTBOX?};
//}}AFX_DATA
//?Implementation
protected:
virtual?void?DoDataExchange(CDataExchange*?pDX);????//?DDX/DDV?support
//{{AFX_MSG
?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\100vhdl例子\
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\100vhdl例子\100vhdl例子\
?????文件??????265994??2017-11-04?12:09??FPGA設計資料\100vhdl例子\100vhdl例子.zip
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\100vhdl例子\100vhdl例子\10_function\
?????文件?????????896??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\10_function\10_bit_to_int.vhd
?????文件?????????101??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\10_function\README.TXT
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\100vhdl例子\100vhdl例子\11_wiredor\
?????文件?????????858??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\11_wiredor\11_wiredor.vhd
?????文件?????????101??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\11_wiredor\README.TXT
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\100vhdl例子\100vhdl例子\12_convert\
?????文件?????????695??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\12_convert\12_convert.vhd
?????文件?????????101??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\12_convert\README.TXT
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\100vhdl例子\100vhdl例子\13_SHL\
?????文件?????????421??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\13_SHL\13_SHL.VHD
?????文件?????????101??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\13_SHL\README.TXT
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\100vhdl例子\100vhdl例子\14_MVL7_functions\
?????文件???????13235??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\14_MVL7_functions\14_MVL7_functions.vhd
?????文件?????????240??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\14_MVL7_functions\README.TXT
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\100vhdl例子\100vhdl例子\15_MUX41\
?????文件????????2055??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\15_MUX41\15_MUX41.VHD
?????文件???????13237??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\15_MUX41\15_MVL7_functions.vhd
?????文件?????????646??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\15_MUX41\15_MVL7_syn_types.vhd
?????文件????????5412??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\15_MUX41\15_test_vectors_mux41.vhd
?????文件???????32169??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\15_MUX41\15_TYPES.VHD
?????文件?????????240??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\15_MUX41\README.TXT
?????目錄???????????0??2018-02-27?19:34??FPGA設計資料\100vhdl例子\100vhdl例子\16_MUX\
?????文件????????1813??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\16_MUX\16_multiple_mux.vhd
?????文件???????13235??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\16_MUX\16_MVL7_functions.vhd
?????文件????????7843??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\16_MUX\16_test_vectors.vhd
?????文件???????32169??2003-02-17?13:06??FPGA設計資料\100vhdl例子\100vhdl例子\16_MUX\16_TYPES.VHD
............此處省略1468個文件信息
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