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資源簡介

基于RGMII的以太網(wǎng)MAC的FPGA實(shí)現(xiàn)代碼,整個工程采用Verilog HDL實(shí)現(xiàn),包括測試用例以及功能驗(yàn)證TestBench

資源截圖

代碼片段和文件信息

clc;clear?all
h?=?crc.generator(‘Polynomial‘[1?0?0?0?0?0?1?0?...
????0?1?1?0?0?0?0?0?...
????1?0?0?0?1?1?1?0?...
????1?1?0?1?1?0?1?1?...
????1]?‘InitialState‘?ones(132));

%??MacPacket=[?...%‘55‘;?‘55‘;‘55‘;‘55‘;‘55‘;?‘55‘;?‘55‘;?‘d5‘;...
%????????????‘11‘;?‘22‘;‘33‘;‘44‘;‘55‘;?‘66‘;...
%????????????‘a(chǎn)a‘;‘bb‘?;‘cc‘;‘dd‘;‘ee‘;?‘ff‘;...
%????????????‘00‘;?‘30‘];

MacPacket=[?...%‘55‘;?‘55‘;‘55‘;‘55‘;‘55‘;?‘55‘;?‘55‘;?‘d5‘;...
????‘50‘;?‘44‘;‘33‘;‘22‘;‘11‘;?‘ee‘;...
????‘22‘;‘33‘?;‘44‘;‘55‘;‘66‘;?‘a(chǎn)a‘;...
????‘00‘;?‘64‘;‘00‘;‘01‘];

CRC32FPGA=[‘91‘;‘f1‘;‘80‘;‘90‘];
Packet=hex2dec(MacPacket);
CRC32FPGA=hex2dec(CRC32FPGA);
Packet=reshape(Packet1length(Packet));
CRC32FPGA=reshape(CRC32FPGA1length(CRC32FPGA));
src=[Packet?0:97];
msg?=?de2bi(src?8?‘right-msb‘);
msg=msg.‘;
msg=msg(:);
encoded=generate(hmsg);%計算的結(jié)果是,低位在前高位在后?與硬件FPGA的計算結(jié)果相反
CRCResult=encoded(end-31:end);
%?CRCResult=flipud(CRCResult);
CRCResult=(CRCResult==0)
x=0;
for?ii=1:length(CRCResult)
????x=x+CRCResult(ii)*2^(ii-1);
end
x
dec2hex(x)
%?msgresult=dec2hex([src?floor(x/256)?mod(x256)])
%?msgresult=msgresult.‘;
%?msgresult=msgresult(:);
%?fid=fopen(‘msgresult.txt‘‘w‘);
%?for?ii=1:length(msgresult)
%?????fprintf(fidmsgresult(ii));
%?????if(mod(ii2)==0)?fprintf(fid‘?‘);
%?????end
%?end
%?fclose(fid);

?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----

?????文件???????6390??2014-04-11?15:57??testbench\harness.v

?????文件?????????20??2011-02-25?17:26??testbench\sim\sim.bat

?????文件????????801??2014-04-11?15:45??testbench\sim\testcase.do

?????文件???????2773??2014-04-11?16:08??testbench\sim\wave.do

?????文件????????607??2013-05-19?17:38??testbench\testcase.v

?????文件???????5900??2014-04-09?18:59??CFG.v

?????文件???????4827??2014-09-16?19:08??GMII.v

?????文件??????17070??2014-09-16?10:35??GMIIReceive.v

?????文件??????21556??2014-09-16?17:18??GMIITransmit.v

?????文件???????4225??2012-06-18?16:32??PN9Check.v

?????文件???????4230??2014-09-16?19:09??RGMII.v

?????文件???????7043??2014-09-16?19:10??RGMII_TEST.v

?????文件????????927??2011-04-20?11:22??VerilogRam.v

?????文件????2104206??2009-10-22?04:11??AteraIPLib\altera_mf.v

?????文件???????3285??2013-12-05?21:06??CRC32\CRC32_D8.v

?????文件???????8923??2013-07-03?20:48??CRC32\doc\CRC16.txt

?????文件?????310784??2013-07-03?21:43??CRC32\doc\CRC16算法分析(資料).doc

?????文件???????3140??2013-12-02?09:18??CRC32\doc\CRC32_D8.v

?????文件?????387377??2013-07-03?15:25??CRC32\doc\CRC_16算法與FPGA實(shí)現(xiàn).pdf

?????文件?????511516??2013-07-03?15:27??CRC32\doc\CRC_16算法及其單片機(jī)實(shí)現(xiàn).pdf

?????文件??????81573??2013-07-03?20:01??CRC32\doc\CRC校驗(yàn)C語言實(shí)現(xiàn).pdf

?????文件????1518262??2013-07-03?15:26??CRC32\doc\基于FPGA的循環(huán)冗余校驗(yàn)并行實(shí)現(xiàn).pdf

?????文件???????1362??2013-12-05?21:19??CRC32\testbench\AlteraCRC32Test.m

?????文件???????1345??2013-12-05?15:35??CRC32\testbench\CRC32.m

?????文件???????3243??2013-12-05?22:46??CRC32\testbench\harness.v

?????文件????????900??2013-12-01?11:28??CRC32\testbench\msgresult.txt

?????文件?????????20??2013-12-05?22:46??CRC32\testbench\SaveFile\FileStoreCRCResult.txt

?????文件??????54879??2013-12-05?22:46??CRC32\testbench\sim\modelsim.ini

?????文件?????????20??2011-02-25?17:26??CRC32\testbench\sim\sim.bat

?????文件????????594??2013-12-01?08:19??CRC32\testbench\sim\testcase.do

............此處省略725個文件信息

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