/**
?*?Using?AXI?Direct?Memory?Access?v7.1
?*?Direct?Register?Mode
?*
?*?Author:?	ZMJ@SEU
?*?Date:?	2016-07-12
?*/

#include?
#include?
#include?
#include?
#include?
#include?
#include?

#define?DMA_base_ADDR	0x40400000		//?Phy.?address?of?axi?dma
#define?DMA_TX_ADDR		0x0F000000		//?Phy.?address?of?TX?buffer
#define?DMA_RX_ADDR		0x0F800000		//?Phy.?address?of?RX?buffer

//?Scatter?/?Gather?Mode?Register?Address?（Non‐Multi?Channel?Mode）
#define?MM2S_DMACR?		0x00		//?MM2S?DMA?Control?Register
#define?MM2S_DMASR?		0x04		//?MM2S?DMA?Status?Register
#define?MM2S_SA?		0x18		//?MM2S?DMA?Source?Address?Register
#define?MM2S_LENGTH?	0x28		//?MM2S?DMA?Transfer?Length?Register
#define?S2MM_DMACR?		0x30		//