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/**
*
*?@file?ps7_init.c
*
*?This?file?is?automatically?generated?
*
*****************************************************************************/

#include?“ps7_init.h“

unsigned?long?ps7_pll_init_data[]?=?{
????//?START:?top
????//?..?START:?SLCR?SETTINGS
????//?..?UNLOCK_KEY?=?0XDF0D
????//?..?==>?0XF8000008[15:0]?=?0x0000DF0DU
????//?..?????==>?MASK?:?0x0000FFFFU????VAL?:?0x0000DF0DU
????//?..?
????EMIT_MASKWRITE（0XF8000008?0x0000FFFFU?0x0000DF0DU）
????//?..?FINISH:?SLCR?SETTINGS
????//?..?START:?PLL?SLCR?REGISTERS
????//?..?..?START:?ARM?PLL?INIT
????//?..?..?PLL_RES?=?0x2
????//?..?..?==>?0XF8

?屬性????????????大小?????日期????時(shí)間???名稱
-----------?---------??----------?-----??----
?????文件????????6263??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\verilog\.svn\text-base\user_logic.v.svn-base
?????文件???????12225??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\verilog\.svn\text-base\cf_clkgen.v.svn-base
?????文件??????????30??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\verilog\.svn\prop-base\user_logic.v.svn-base
?????文件??????????30??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\verilog\.svn\prop-base\cf_clkgen.v.svn-base
?????文件????????9592??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\vhdl\.svn\text-base\axi_clkgen.vhd.svn-base
?????文件??????????30??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\vhdl\.svn\prop-base\axi_clkgen.vhd.svn-base
?????文件????????6152??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\.svn\text-base\tx_package.vhd.svn-base
?????文件???????20871??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\.svn\text-base\tx_encoder.vhd.svn-base
?????文件???????13720??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\.svn\text-base\axi_spdif_tx.vhd.svn-base
?????文件????????5012??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\.svn\text-base\tx_bitbuf.vhd.svn-base
?????文件???????17875??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\.svn\text-base\user_logic.vhd.svn-base
?????文件?????????586??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\verilog\.svn\entries
?????文件?????????426??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\vhdl\.svn\entries
?????文件????????1488??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\data\.svn\text-base\_axi_clkgen_xst.prj.svn-base
?????文件?????????565??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\data\.svn\text-base\axi_clkgen_v2_1_0.pao.svn-base
?????文件????????2843??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\data\.svn\text-base\axi_clkgen_v2_1_0.mpd.svn-base
?????文件??????????30??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\data\.svn\prop-base\_axi_clkgen_xst.prj.svn-base
?????文件??????????30??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\data\.svn\prop-base\axi_clkgen_v2_1_0.pao.svn-base
?????文件??????????30??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\data\.svn\prop-base\axi_clkgen_v2_1_0.mpd.svn-base
?????文件????????1031??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\.svn\entries
?????文件????????1433??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\data\.svn\text-base\_axi_spdif_tx_xst.prj.svn-base
?????文件?????????689??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\data\.svn\text-base\axi_spdif_tx_v2_1_0.pao.svn-base
?????文件????????3534??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\data\.svn\text-base\axi_spdif_tx_v2_1_0.mpd.svn-base
?????文件????????6263??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\verilog\user_logic.v
?????文件???????12225??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\verilog\cf_clkgen.v
?????文件????????9592??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\hdl\vhdl\axi_clkgen.vhd
?????文件?????????762??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_clkgen_v1_00_a\data\.svn\entries
?????文件????????6152??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\tx_package.vhd
?????文件????????5012??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\tx_bitbuf.vhd
?????文件???????20871??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\tx_encoder.vhd
?????文件???????17875??2012-07-11?22:46??ZedBoard_OOB_Design\hw\xps_proj\pcores\axi_spdif_tx_v1_00_a\hdl\vhdl\user_logic.vhd
............此處省略197個(gè)文件信息