?屬性????????????大小?????日期????時(shí)間???名稱
-----------?---------??----------?-----??----

?????文件????????500??2005-01-28?02:44??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\AndOr.v

?????文件???????1988??2008-01-18?00:30??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Intro_Top.sct

?????文件???????1147??2005-02-15?12:49??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Intro_Top.spj

?????文件???????1288??2005-09-21?08:48??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Intro_Top.v

?????文件?????????56??2005-01-28?02:45??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Intro_Top.vcs

?????文件????????500??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\AndOr.v

?????文件???????1382??2007-01-31?03:59??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\default.cfg

?????文件???????1028??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\Intro_Netlist.v

?????文件???????1990??2008-01-18?00:30??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\Intro_Top.sct

?????文件???????2980??2007-11-20?05:13??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\Intro_Top.SDF

?????文件???????1147??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\Intro_Top.spj

?????文件???????1288??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\Intro_Top.v

?????文件?????????56??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\Intro_Top.vcs

?????文件???????3795??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\Intro_TopFlat.sdf

?????文件????????609??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\Intro_TopFlat.v

?????文件????????741??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\SR.v

?????文件???????1633??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\TestBench.v

?????文件???????1598??2007-11-20?04:46??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\VCS_SimRun.VCD

?????文件????????665??2007-09-19?03:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\Lab01_Ans\XorNor.v

?????文件????????741??2005-04-10?04:38??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\SR.v

?????文件???????1633??2005-08-23?09:48??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\TestBench.v

?????文件????????665??2007-09-19?02:44??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab01\XorNor.v

?????文件???????1204??2007-09-19?03:44??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab02\Lab02_Ans\default.cfg

?????文件????????559??2005-02-15?12:39??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab02\Lab02_Ans\Extend.spj

?????文件???????1224??2005-11-03?07:12??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab02\Lab02_Ans\Extend.v

?????文件????????869??2005-02-15?12:40??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab02\Lab02_Ans\Vector.spj

?????文件???????1288??2007-09-19?03:48??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab02\Lab02_Ans\Vector.v

?????文件???????1217??2005-02-01?03:32??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab03\Converter.v

?????文件???????1105??2005-02-15?12:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab03\Counter.spj

?????文件???????1510??2005-08-24?04:34??Verilog數(shù)字VLSI設(shè)計(jì)教程\Lab03\Counter.v

............此處省略1660個(gè)文件信息