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淺談ov7670的基礎(chǔ)知識(shí)和寄存器配置,適合新手入門(mén)閱讀
艾曼電子披術(shù)文襠 2013-2-21 Http://amfpga.TaobaO.cOm Power supply (VDD-C- 1.8 VDC +10%)for digital 15 DVDD Power output drive 16 HREF Output HREF output Power Down Mode Selection- active high, internal Function PWDN pull-down resistor. 0: Normal mode 1: Power down (default=0) mo 18 VSYNC Output Vertical sync output Clears all registers and resets them to their Function 19 RESET default values. Active high, internal pull-down (default= 0) resistor 20 SIO C Input SCCB serial interface clock input AVDD Power Analog power supply (VDD-A-2 45 to 2.8 VDC) 22 SIO D T/0 SCCB serial interface data 1/0 AGND Power nalog ground 24 2.Ov7670功能模塊圖 3/23 曼電子披術(shù)文檔 2013-2-21http://amfpga.taObao.Com 1 Generator 3 eheegscalerFIFoVideo DSP Port D[:0 5060Hz Aute wnNe SLr Column Sense Amp 日 xposure/Gain 4 Video Timing Generator SCCB Interface XCLK STROBE HREF PCLK VSYNC RESETE PWDN SIO C SIO D 圖3oV7670功能模塊圖(源自于OV7670 Preliminary Datasheet Version1.4Page2) 由圖3可知,模塊由5大部分構(gòu)成,分別是,1:圖像模數(shù)轉(zhuǎn)換( Analog processing);2: 測(cè)試圖案發(fā)生器( Test Pattern generator);3:數(shù)據(jù)輸出;4:656X488圖像傳感器整列;5: SCCB通信接口。 3.1 Image Sensor Array Ov7670傳感器陣列為656X488,總共有320,128像素點(diǎn),其中有效的為640X480, 總共是307,200像素。 2.2 Timing generator 有以下功能 1)圖像陣刎控制和圖像幀產(chǎn)生 2)內(nèi)部時(shí)序信號(hào)產(chǎn)生和分發(fā) )幀率時(shí)序 4)自動(dòng)曝光控制(AEC)相關(guān)寄存器 (COM1=0x04: AECHH=OXO7: AECH=Ox10, COM8=0x13) 5)外部時(shí)序輸出( VSYNCHREF/ HSYNO,和PCLK) 4/23 艾曼電子披術(shù)文襠 2013-2-21 Http://amfpga.TaobaO.cOm oV7670攝像頭怎么用 1.攝像頭硬件電路 所使用攝像頭的電路原理圖如圖4所示。U1為OV7670攝像頭傳感器,采用BGA 封裝。P1為外部接口,信號(hào)電平為33VTTL,可以跟3.3V電平的外設(shè)直接連接。 VCC為33V電壓。在電路上特別要注意的是,SCCB的兩根信號(hào)線SO_D,SOC需 要上拉47K電阻。圖5為攝像頭模塊實(shí)物圖 UI VCC AVDD SIO D A2AVDD SIO C SIO D asSOc DinAS GND VREF AGND B GND D2 PCLK IRER STROBE E1 PCLK STRO XCLK E4 ⅩCLK DOVDD RESET# SIO C DOGND RESET# F3 DOGND F4 VREE2 . r4 DVDD GAD 104 VREFI 104 VC 經(jīng): XCLK 10 D6 12 16 圖4OV7670攝像頭模塊電路原理圖 /23 曼電子披術(shù)文檔 2013-2-21http://amfpga.taObao.Com C1 C2R1 O:H O REU.1 C8 2oooooooop6 ao0ooooos 圖50v7670攝像頭模塊實(shí)物圖 2.O7670接口時(shí)序 OV7670接口時(shí)序包括兩部分:1)SCCB接口時(shí)序;2)圖像數(shù)據(jù)輸出時(shí)序; 21SCCB接口 2-Wire SCCB Functional Block Diagram SIO C Master Device SIO D Slave Device 圖6SCCB功能圖 SCB是歐姆尼圖像技術(shù)公司( Omnivision)開(kāi)發(fā)的一科總線,并廣泛的應(yīng)用于0V系列圖 像傳感器上。SCCB是一種3線的總線,它由 SCCB E、SI0C、SI0D組成。在為了減少引腳的芯 片上縮減為2根線,SI0C和SI0D。 2.2起始和終止時(shí)序 Start of Transmission SCCB E SIO C PRC SIO 圖7SCCB起始信號(hào) 6/23 曼電子披術(shù)文檔 2013-2-21http://amfpga.taObao.Com 在啟動(dòng)傳輸過(guò)程中有兩個(gè)時(shí)間參數(shù),tPRA和tPRC,tPRC被定義為SIoD預(yù)充電時(shí)間,這表 明SIOD必須先于 SCCB E被拉高的時(shí)間,最小值為15ns,tPRA被是指在SIO_D拉低之 前,SIOE被拉低的時(shí)間,不能小于1.25us。 數(shù)據(jù)傳輸?shù)慕K止 Transmission SCCB E SIO C Psc SIO D 圖8SCCB終止信號(hào) tPSC是SCCB-一E上升沿,SIO_D保持邏輯高電平的時(shí)間,最小為15ns; tPsA是SIo_D上升沿, SCCB E必須保持低電平的時(shí)間,最小為0ns 2.3SCCB寫(xiě)時(shí)序 寫(xiě)時(shí)序由3相構(gòu)成。先寫(xiě)設(shè)各地址,再寫(xiě)寄存器地址,最后寫(xiě)寄存器的值,即1 D-Address+SUB- Address +W-Data.OV7670的設(shè)備地址為0x42,最后一位用來(lái)判斷讀寫(xiě),即讀的時(shí)候?yàn)?×43 3-Phase Write Transmission Cycle 0一 Phase 1 Phase 2 Phase 3 Phase 1-ID Address ase SCCB E SIO C 0: Write 1: Read SIO D SICO OE M SI00 OE S 7/23 曼電子披術(shù)文檔 2013-2-21http://amfpga.taObao.Com Phase 2- Sub-address(3-Phase Write Transmission) Phase 2 SCCB E SIO0 OE M SIO0 OE S 圖9SCCB讀寫(xiě)傳輸時(shí)序圖 每次發(fā)送8個(gè)數(shù)據(jù),SDAT設(shè)置為輸入,接收一個(gè)從機(jī)反饋的信號(hào)。依次發(fā)送ID- Address+SUB- Address+ W-Data 2.4SCCB讀時(shí)序 讀時(shí)序由4相構(gòu)成,分別是 ID Address+Sub- Address+ ID Address+ Read data。 2-Phase Write Transmission Cycle 2-Phase Read transmission cycle ID Address Sub-address ID Address Read Dat Phase 1 Phase 2 Phase 1 Phase 2 手冊(cè)中特別提到, There must be either a 3-phase or a 2-phase write transmission cycle asserted ahead of a 2-phase read transmission cycle. The 2-phase read transmission cycle(see Figure 3-7) has no ability to identify the sub-address. The 2-phase write transmission cycle contains read data of 8 bits and a ninth Don' t-Care bit or na bit The master must drive the na bit at logical 1 也就是在 Read data環(huán)節(jié)里,有個(gè)NA,即第9位要驅(qū)動(dòng)S|O_D為高電平 3.SCCB的 Verilog程序解析 if(WR) //12C Write: ID-Address SUB-Address +w-Data hegIn case(SD COUNTEr) //IDLE 6do begin SCLK <=1: 2CB|T<=1 8/23 艾曼電子披術(shù)文襠 2013-2-21 Http://amfpga.TaobaO.cOm ACKW1<=1: ACKW2<=1, ACKW3<=1: ACKR1<=1: ACKR2<=1: ACKR3<=1: END<=O end //Start 6d1: begi SCLK <=1. 12C_BT<=1; ACKW1<=1: ACKW2<=1, ACKW3<=1 END <=O e 6d2:|2CBT<=0; //12C SDAT=0 6d3 SCLK<=0 //12C SCLK=0 //SLAVE ADDR--ACK1 6d4 12C_BIT <= 12C_WDATA[23]; //Bit8 6'd5 12C BIT<=12C WDATA[22]; //Bit7 6d6: 12C BIT<=12C WDATA[21]; //Bit6 6'd7 12C BIT <=12C WDATA[20]; //Bit5 6d8:12C8T<=2 WDATA[9;/|t4 6 d9 12C BIT <=12C WDATA[18];//Bit3 6d10: 12C bIT < |2C WDaTA[17 ;//Bit2 6d11: 12C BIT <=12C WDATA[16];//Bit1 6d12:|2CBT<=0; //High-Z, Input 6d13: ACKW1 <=12C SDAT //ACK1 6'd14:2CBT<=0 //Delay //SUB ADDR--ACK2 9/23 艾曼電子披術(shù)文襠 2013-2-21 Http://amfpga.TaobaO.cOm 6'd15: 12C_BIT <=12C_ WDATA[15]; //Bit8 6'd16: 12C_ BIT <=12C_WDATA[14]; //Bit7 6'd17: 12C_BIT <=12C_WDATA[13]; //Bit6 6'd18: 12C_BIT <=12C_WDATA[12]; //Bit5 6d19:12C_BT<=12 C WDATA[11];//Bt4 6'd20: 12C BIT <=12C WDATA[10]; //Bit3 6'd21: 12C BIT < 12C WdatA[9];//Bit2 6'd22: 12C_BIT <=12C WDATA[8];//Bit1 6d23:2CBT<=0: //High-Z, Input 6'd24: ACKW2 <=12C SDAT; // ACK2 6′d25:|2CB|T<=0; //Delay //rite DATA--ACK3 6'd26: 12C_BIT<=12C WDATA[]: / Bit 6d27:2C_BT<=12C_ WDATA[6];//Bt7 6'd28: 12C_ BIT <=12C WDATA[5]; //Bit6 6'd29: 12C BIT <=12C WDATA[4];// Bit5 6'd30: 12C BIT < 12C WDATA[3];//Bit4 6'd31: 12C_ BIT <=12C WDATA[2];//Bit3 6'd32: 12C BIT <=12C WDATA[1];//Bit2 6'd33: 12C BIT<=12C WDATA[O]//Bit1 6d34:2CBT<=0; //High-Z, Input 6′d35:ACKW3 := 12C SDAT //ACK3 6d36:|2CBT<=0; //Delat //St 6'd37: begin SCLK <=0; 12C_ BIT <=0; end 6d38: SCLK < 1: 10/23
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