講述了SPI總線原理，提供主從設(shè)備Verilog源碼及仿真波形，對(duì)初學(xué)者有幫助
淘寶店鋪:小月電子 QQ:3181961725 lways@ (posedge sysclkspi clk r<= spi clk ∥/從機(jī)讀取數(shù)據(jù),MSO串轉(zhuǎn)并 always@(posedge sysclk or negedge rst n begin (!rst_ n) egin nt data in<= 4do shift reg<= 8'dz data bus <=8dz Vi <=1"b0; else if (cnt data in ==8) be cnt data in <=0 data b 1b1; else if( spi clk_neg∥/下降沿讀取數(shù)據(jù) egir va|<=1"b0 data bus <=8d cnt data in<= cnt data in+1 b1 hift_reg<=Shift reg[6: 0], misoF end els /向從機(jī)寫(xiě)數(shù)據(jù),并轉(zhuǎn)串MOS,高位在前 always@(posedge sysclk or negedge rst n begin if (rst n begin cnt data send 4′d0 shift send 8'h else if( cnt data send==8) begin cnt data send <= 4d0 shift send <=8 haa: end else if(spi_ck_pos)/上升沿發(fā)送數(shù)據(jù) gIn mosi < shift send[7]: 淘寶店鋪:小月電子 Qa:3181961725 淘寶店鋪:小月電子 QQ:3181961725 shift send <=(shift send[6: 0], b01 nt data send cnt data send +1b1 eIst end module sP從設(shè)備 Verilog源碼 module spi slave( input sysc nput n put outpu eg mIso input lk output reg 7: 0] data inout g spi clk ri reg [3: 0] cnt send g[7: 0 data send g [3: 0 cnt rece reg [7: 0 receive reg lways @ posedge sysclk spi clk r <=spi clk sign pos spi clk =(spi clk r& spi_clk ) assign neg_ spi clk =(spi clk spi clk r) always@(posedge sysclk or negedge rst n) begin if(!rst_n egIn cnt send <=4'd0 data send 8d170; nd Ise if(cnt send ==8 egIn cnt send data send <=8hba end else if(pos spi clk egIn cnt send < cnt send +1b1 d[刀 data send <=data send[6: 0],1'b0J: else 淘寶店鋪:小月電子 Qa:3181961725 淘寶店鋪:小月電子 QQ:3181961725 end always@(posedge sysclk or negedge rst n) begin if(!rst n) begin cnt receive < 4'd0 receive reg <=do data inout <=8'dz end else if (cnt receive ==8 egIn data inout < receive regi else if(neg spi clk&&Cs==o) begil cnt receive < cnt receive +1 b1 receive reg <=receive_ reg[6: 0], mosi] data inout<='dz end else endmodule 仿真波形圖: 主設(shè)備向從設(shè)備發(fā)送0xaa,從設(shè)備向主設(shè)備發(fā)送0xab 1 U. ILIUL LILTIILULm. T uL UIUU MI MIILLULLLLLOLIL LILmm uTuu MU ILLIL LuLILLIL umU uunuMLULILIO MIUI ≌ achive rec I':0 淘寶店鋪:小月電子 Qa:3181961725