資源簡介
利用verilog實現的四位節省進位乘法器,最大延時為3.372ns,資源為16個LUT
代碼片段和文件信息
?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????文件????????160??2013-05-03?16:17??mul\addr.v
?????文件????????160??2013-05-05?11:31??mul\addr1.v
?????文件????????500??2013-05-05?11:26??mul\addr_3.v
?????文件????????113??2013-05-05?21:30??mul\addr_half.v
?????文件????????150??2013-05-05?11:04??mul\mu.v
?????文件???????1086??2013-05-05?20:55??mul\mul.v
?????文件????????148??2013-05-05?11:30??mul\mu_half.v
?????文件????????128??2013-05-05?10:58??mul\yu.v
?????文件????????121??2013-05-05?20:53??mul\yu1.v
?????目錄??????????0??2013-05-05?21:56??mul
-----------?---------??----------?-----??----
?????????????????2566????????????????????10
-----------?---------??----------?-----??----
?????文件????????160??2013-05-03?16:17??mul\addr.v
?????文件????????160??2013-05-05?11:31??mul\addr1.v
?????文件????????500??2013-05-05?11:26??mul\addr_3.v
?????文件????????113??2013-05-05?21:30??mul\addr_half.v
?????文件????????150??2013-05-05?11:04??mul\mu.v
?????文件???????1086??2013-05-05?20:55??mul\mul.v
?????文件????????148??2013-05-05?11:30??mul\mu_half.v
?????文件????????128??2013-05-05?10:58??mul\yu.v
?????文件????????121??2013-05-05?20:53??mul\yu1.v
?????目錄??????????0??2013-05-05?21:56??mul
-----------?---------??----------?-----??----
?????????????????2566????????????????????10
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