?屬性????????????大小?????日期????時間???名稱
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?????目錄??????????0??2007-04-27?10:36??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469

?????目錄??????????0??2006-07-17?11:49??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章

?????目錄??????????0??2006-07-17?11:49??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1

?????文件???????1563??2006-07-17?11:50??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\subtracter_1.qpf

?????文件???????2471??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\subtracter_1.qsf

?????目錄??????????0??2006-07-17?11:50??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db

?????文件????????136??2006-07-17?11:50??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.db_info

?????文件???????4745??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.cmp.hdb

?????文件???????6988??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.cmp.rdb

?????文件???????1347??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.sim.qmsg

?????文件????????858??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.hif

?????文件???????2191??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.sim.hdb

?????文件????????148??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.cmp.ddb

?????文件???????4314??2006-07-17?13:06??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.sim.vwf

?????文件???????1707??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.sim.rdb

?????文件????????223??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.hier_info

?????文件????????134??2006-07-17?13:09??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.sld_design_entry.sci

?????文件????????142??2006-07-17?13:09??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.eco.cdb

?????文件??????????0??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.psp

?????文件??????????0??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.syn_hier_info

?????文件??????????0??2006-07-17?11:57??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1_cmp.qrpt

?????文件??????????3??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.eds_overflow

?????文件??????????0??2006-07-17?12:00??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1_sim.qrpt

?????文件???????1921??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.map.qmsg

?????文件????????906??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.（0）.cnf.cdb

?????文件????????422??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.（0）.cnf.hdb

?????文件????????924??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.rtlv_sg.cdb

?????文件???????4764??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.rtlv.hdb

?????文件????????158??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.rtlv_sg_swap.cdb

?????文件???????4776??2006-07-17?13:05??《Verilog?HDL數(shù)字控制系統(tǒng)設(shè)計實例》-冼進(jìn)-源代碼-4469\第1章\subtracter_1\db\subtracter_1.pre_map.hdb

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