資源簡介
本項目主要利用Verilog語言設計一一個基于MIPS架構的CPU。分別設計指令存儲器、寄存器堆、ALU、取指令部件、數據存儲器、立即數處理單元、主單元控制器、ALU控制單元。將這些單元連城數據通路，再結合控制單元合成CPU下板驗證。并基于該cpu完成了串口收發數據的驅動，并下板測試，功能正確。該代碼是基于EP4CE10F17C8開發板的，可直接下板，其他開發板只需稍做改變即可用
代碼片段和文件信息
?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????目錄???????????0??2018-06-26?19:31??cpu_uart\
?????目錄???????????0??2018-06-26?22:04??cpu_uart\design\
?????文件?????????753??2018-04-11?19:41??cpu_uart\design\add.v
?????文件????????1413??2018-05-29?15:17??cpu_uart\design\addsub32.v
?????文件????????2983??2018-06-26?21:43??cpu_uart\design\alu.v
?????文件????????2738??2018-05-16?18:16??cpu_uart\design\alu.v.bak
?????文件?????????775??2018-05-02?17:59??cpu_uart\design\alu_src_mux2.v
?????文件?????????745??2018-05-11?08:24??cpu_uart\design\barrel_shifter.v
?????文件?????????769??2018-04-11?19:44??cpu_uart\design\cla32.v
?????文件?????????901??2017-04-27?17:05??cpu_uart\design\cla_16.v
?????文件?????????878??2017-04-27?17:05??cpu_uart\design\cla_2.v
?????文件?????????907??2017-04-27?17:05??cpu_uart\design\cla_32.v
?????文件?????????892??2017-04-27?17:05??cpu_uart\design\cla_4.v
?????文件?????????894??2017-04-27?17:05??cpu_uart\design\cla_8.v
?????文件????????6027??2018-06-27?09:27??cpu_uart\design\contro_signall.v
?????文件????????5120??2018-05-16?18:04??cpu_uart\design\contro_signall.v.bak
?????文件????????1460??2018-05-14?15:06??cpu_uart\design\ctrl.v
?????文件?????????863??2017-04-27?16:30??cpu_uart\design\g_p.v
?????文件?????????335??2018-05-02?16:02??cpu_uart\design\imm_ext.v
?????文件????????2871??2018-06-27?09:33??cpu_uart\design\instr_memory.v
?????文件?????????968??2018-05-15?18:45??cpu_uart\design\instr_memory.v.bak
?????文件????????1152??2018-06-26?20:54??cpu_uart\design\jicunqi.v
?????文件????????1031??2018-05-14?18:16??cpu_uart\design\jicunqi.v.bak
?????文件????????6883??2018-03-20?20:03??cpu_uart\design\line.v
?????文件?????????799??2018-05-02?17:51??cpu_uart\design\mem_to_reg_mux2.v
?????文件????????5553??2018-04-17?09:35??cpu_uart\design\mul.v
?????文件?????????531??2018-05-16?16:33??cpu_uart\design\mux4.v
?????文件????????1020??2018-05-12?08:24??cpu_uart\design\mux_signed.v
?????文件????????1173??2018-03-27?14:39??cpu_uart\design\one.v
?????文件?????????768??2018-04-26?18:11??cpu_uart\design\pc.v
?????文件?????????680??2018-05-03?16:20??cpu_uart\design\pc_addr.v
............此處省略254個文件信息
-----------?---------??----------?-----??----
?????目錄???????????0??2018-06-26?19:31??cpu_uart\
?????目錄???????????0??2018-06-26?22:04??cpu_uart\design\
?????文件?????????753??2018-04-11?19:41??cpu_uart\design\add.v
?????文件????????1413??2018-05-29?15:17??cpu_uart\design\addsub32.v
?????文件????????2983??2018-06-26?21:43??cpu_uart\design\alu.v
?????文件????????2738??2018-05-16?18:16??cpu_uart\design\alu.v.bak
?????文件?????????775??2018-05-02?17:59??cpu_uart\design\alu_src_mux2.v
?????文件?????????745??2018-05-11?08:24??cpu_uart\design\barrel_shifter.v
?????文件?????????769??2018-04-11?19:44??cpu_uart\design\cla32.v
?????文件?????????901??2017-04-27?17:05??cpu_uart\design\cla_16.v
?????文件?????????878??2017-04-27?17:05??cpu_uart\design\cla_2.v
?????文件?????????907??2017-04-27?17:05??cpu_uart\design\cla_32.v
?????文件?????????892??2017-04-27?17:05??cpu_uart\design\cla_4.v
?????文件?????????894??2017-04-27?17:05??cpu_uart\design\cla_8.v
?????文件????????6027??2018-06-27?09:27??cpu_uart\design\contro_signall.v
?????文件????????5120??2018-05-16?18:04??cpu_uart\design\contro_signall.v.bak
?????文件????????1460??2018-05-14?15:06??cpu_uart\design\ctrl.v
?????文件?????????863??2017-04-27?16:30??cpu_uart\design\g_p.v
?????文件?????????335??2018-05-02?16:02??cpu_uart\design\imm_ext.v
?????文件????????2871??2018-06-27?09:33??cpu_uart\design\instr_memory.v
?????文件?????????968??2018-05-15?18:45??cpu_uart\design\instr_memory.v.bak
?????文件????????1152??2018-06-26?20:54??cpu_uart\design\jicunqi.v
?????文件????????1031??2018-05-14?18:16??cpu_uart\design\jicunqi.v.bak
?????文件????????6883??2018-03-20?20:03??cpu_uart\design\line.v
?????文件?????????799??2018-05-02?17:51??cpu_uart\design\mem_to_reg_mux2.v
?????文件????????5553??2018-04-17?09:35??cpu_uart\design\mul.v
?????文件?????????531??2018-05-16?16:33??cpu_uart\design\mux4.v
?????文件????????1020??2018-05-12?08:24??cpu_uart\design\mux_signed.v
?????文件????????1173??2018-03-27?14:39??cpu_uart\design\one.v
?????文件?????????768??2018-04-26?18:11??cpu_uart\design\pc.v
?????文件?????????680??2018-05-03?16:20??cpu_uart\design\pc_addr.v
............此處省略254個文件信息
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