這是一本關于數字電路的測試以及可測性的書，其中測試部分用設計語言描述出來。這本書展示了如何采用一些已建立的RTL級設計來測試數字電路。本書主要采用Verilog HDL模型建立測試，具有較好的實踐性。 This is a book on test and testability of digital circuits in which test is spoken in the language of design. In this book, the concepts of testing and testability are treated together with digital design practices and methodologies. We show how testing digital circuits designing testable circuits can take advantage of some of the well-established RT-level design and verification methodologies and tools. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. In the testability part, it describes various scan and BIST methods in Verilog and uses Verilog testbenches as virtual testers to examine and evaluate these testability methods. In designing testable circuits, we use Verilog testbenches to evaluate, and thus improve testability of a design.