資源簡介
用verilog編寫的LVDS接口驅動程序，采用IOSERDES技術實現，經過Spartan6 FPGA調試驗證，有完整的工程。
代碼片段和文件信息
?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????文件???????7878??2019-02-18?17:16??source\lvds_ctr_top.v
?????文件??????12423??2017-09-23?16:49??source\parallel_to_serial.v
?????文件???????2350??2018-08-10?14:38??source\RXSerialData_ctr.v
?????文件??????10524??2017-09-22?11:14??source\serial_to_parallel.v
?????文件???????2224??2018-08-10?14:26??source\TXParaData_ctr.v
?????目錄??????????0??2017-09-28?10:31??source
-----------?---------??----------?-----??----
????????????????35399????????????????????6
-----------?---------??----------?-----??----
?????文件???????7878??2019-02-18?17:16??source\lvds_ctr_top.v
?????文件??????12423??2017-09-23?16:49??source\parallel_to_serial.v
?????文件???????2350??2018-08-10?14:38??source\RXSerialData_ctr.v
?????文件??????10524??2017-09-22?11:14??source\serial_to_parallel.v
?????文件???????2224??2018-08-10?14:26??source\TXParaData_ctr.v
?????目錄??????????0??2017-09-28?10:31??source
-----------?---------??----------?-----??----
????????????????35399????????????????????6
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