#!/usr/bin/env?python3
#
#?DVB?FPGA
#
#?Copyright?2019?by?Suoto?
#
#?This?file?is?part?of?DVB?FPGA.
#
#?DVB?FPGA?is?free?software:?you?can?redistribute?it?and/or?modify
#?it?under?the?terms?of?the?GNU?General?Public?License?as?published?by
#?the?Free?Software?Foundation?either?version?3?of?the?License?or
#?（at?your?option）?any?later?version.
#
#?DVB?FPGA?is?distributed?in?the?hope?that?it?will?be?useful
#?but?WITHOUT?ANY?WARRANTY;?without?even?the?implied?warranty?of
#?MERCHANTABILITY?or?FITNESS?FOR?A?PARTICULAR?PURPOSE.??See?the
#?GNU?General?Public?License?for?more?details.
#
#?You?should?have?received?a?copy?of?the?GNU?General?Public?License
#?along?with?DVB?FPGA.??If?not?see?.
“VUnit?test?runner?for?DVB?FPGA“

#?pylint:?disable=bad-continuation

import?logging
import?os.path?as?p
import?random
import?struct
import?sys
from?enum?import?Enum

from?vunit?import?VUnit??#?type:?ignore

_logger?=?logging.getLogger（__name__）


ROOT?=?p.abspath（p.dirname（__file__））


def?main（）:
????“Main?entry?point?for?DVB?FPGA?test?runner“
????cli?=?VUnit.from_argv（）
????cli.add_osvvm（）
????cli.add_com（）
????cli.enable_location_preprocessing（）

????library?=?cli.add_library（“lib“）
????library.add_source_files（p.join（ROOT?“rtl“?“*.vhd“））
????library.add_source_files（p.join（ROOT?“rtl“?“bch_generated“?“*.vhd“））

????library.add_source_files（p.join（ROOT?“testbench“?“*.vhd“））
????library.add_source_files（p.join（ROOT?“testbench“?“*“?“*.vhd“））

????cli.add_library（“str_format“）.add_source_files（
????????p.join（ROOT?“third_party“?“hdl_string_format“?“src“?“*.vhd“）
????）

????addAllConfigsTest（
????????entity=cli.library（“lib“）.entity（“axi_bch_encoder_tb“）
????????input_file_basename=“bch_encoder_input.bin“
????????reference_file_basename=“ldpc_encoder_input.bin“
????）

????addAllConfigsTest（
????????entity=cli.library（“lib“）.entity（“axi_bit_interleaver_tb“）
????????input_file_basename=“bit_interleaver_input.bin“
????????reference_file_basename=“bit_interleaver_output.bin“
????）

????addAllConfigsTest（
????????entity=cli.library（“lib“）.entity（“axi_baseband_scrambler_tb“）
????????input_file_basename=“bb_scrambler_input.bin“
????????reference_file_basename=“bch_encoder_input.bin“
????）

????parametrizeTests（
????????entity=cli.library（“lib“）.entity（“axi_bch_encoder_tb“）
????????input_file_basename=“bch_encoder_input.bin“
????????reference_file_basename=“ldpc_encoder_input.bin“
????）

????parametrizeTests（
????????entity=cli.library（“lib“）.entity（“axi_bit_interleaver_tb“）
????????input_file_basename=“bit_interleaver_input.bin“
????????reference_file_basename=“bit_interleaver_output.bin“
????）

????addAxiStreamDelayTests（cli.library（“lib“）.entity（“axi_stream_delay_tb“））
????addAxiFileReaderTests（cli.library（“lib“）.entity（“axi_file_reader_tb“））
????addAxiFileCompareTests（cli.library（“lib“）.entity（“axi_file_compare_tb“））

????cli.set_compile_option（“modelsim.vcom_flags“?[“-explicit“]）
????cli.set

?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????目錄???????????0??2020-01-29?20:27??dvb_fpga-master\
?????目錄???????????0??2020-01-29?20:27??dvb_fpga-master\.github\
?????目錄???????????0??2020-01-29?20:27??dvb_fpga-master\.github\workflows\
?????文件?????????331??2020-01-29?20:27??dvb_fpga-master\.github\workflows\push.yml
?????文件??????????41??2020-01-29?20:27??dvb_fpga-master\.gitignore
?????文件?????????132??2020-01-29?20:27??dvb_fpga-master\.gitmodules
?????文件?????????299??2020-01-29?20:27??dvb_fpga-master\.hdl_checker.config
?????文件???????35149??2020-01-29?20:27??dvb_fpga-master\LICENSE
?????文件????????4538??2020-01-29?20:27??dvb_fpga-master\README.md
?????目錄???????????0??2020-01-29?20:27??dvb_fpga-master\docker\
?????文件????????1046??2020-01-29?20:27??dvb_fpga-master\docker\Dockerfile
?????文件????????1286??2020-01-29?20:27??dvb_fpga-master\docker\docker_entry_point.sh
?????文件????????1601??2020-01-29?20:27??dvb_fpga-master\docker\run_tests.sh
?????目錄???????????0??2020-01-29?20:27??dvb_fpga-master\gnuradio_data\
?????文件????????1083??2020-01-29?20:27??dvb_fpga-master\gnuradio_data\Makefile
?????文件???????72662??2020-01-29?20:27??dvb_fpga-master\gnuradio_data\dvbs2_frame_sync.grc
?????文件???????15461??2020-01-29?20:27??dvb_fpga-master\gnuradio_data\dvbs2_tx.py
?????目錄???????????0??2020-01-29?20:27??dvb_fpga-master\misc\
?????文件??????146175??2020-01-29?20:27??dvb_fpga-master\misc\system_architecture.png
?????目錄???????????0??2020-01-29?20:27??dvb_fpga-master\rtl\
?????文件????????3416??2020-01-29?20:27??dvb_fpga-master\rtl\axi_baseband_scrambler.vhd
?????文件????????9388??2020-01-29?20:27??dvb_fpga-master\rtl\axi_bch_encoder.vhd
?????文件???????24557??2020-01-29?20:27??dvb_fpga-master\rtl\axi_bit_interleaver.vhd
?????文件????????3208??2020-01-29?20:27??dvb_fpga-master\rtl\axi_stream_delay.vhd
?????文件????????5898??2020-01-29?20:27??dvb_fpga-master\rtl\axi_stream_fifo.vhd
?????文件????????4727??2020-01-29?20:27??dvb_fpga-master\rtl\axi_stream_master_adapter.vhd
?????文件????????8499??2020-01-29?20:27??dvb_fpga-master\rtl\bch_encoder_mux.vhd
?????目錄???????????0??2020-01-29?20:27??dvb_fpga-master\rtl\bch_generated\
?????文件???????54081??2020-01-29?20:27??dvb_fpga-master\rtl\bch_generated\bch_128x16.vhd
?????文件???????97591??2020-01-29?20:27??dvb_fpga-master\rtl\bch_generated\bch_128x32.vhd
?????文件??????194999??2020-01-29?20:27??dvb_fpga-master\rtl\bch_generated\bch_128x64.vhd
............此處省略35個文件信息