%頻偏：-60Hz
%相偏：在0－－2*pi內隨機分布

%程序及結果如下：
clear?all;
close?all;
%定義鎖相環的工作模式：單載波為“1”、BPSK調制為“2”、QPSK調制為“3”
PLL_Mode?=?2;
%仿真數據長度
Simulation_Length=1000;
%基帶信號
if?PLL_Mode?==?1
I_Data=ones（Simulation_Length1）;
Q_Data=I_Data;
else?if?PLL_Mode?==?2
I_Data=randint（Simulation_Length1）*2-1;
Q_Data=zeros（Simulation_Length1）;
else
I_Data=randint（Simulation_Length1）*2-1;
Q_Data=randint（Simulation_Length1）*2-1;
end
end
Signal_Source=I_Data?+?j*Q_Data;



%載波信號
Freq_Sample=2400;%采樣率，Hz
Delta_Freq=-60;?%頻偏，Hz
Time_Sample=1/Freq_Sample;
Delta_Phase=rand（1）*2*pi;?%隨機初相，Rad
Carrier=exp（j*（Delta_Freq/Freq_Sample*（1:Simulation_Length）+Delta_Phase））;
%調制處理
Signal_Channel=Signal_Source.*Carrier‘;

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%以下為鎖相環處理過程
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%參數清零
Signal_PLL=zeros（Simulation_Length1）;
NCO_Phase?=?zeros（Simulation_Length1）;
Discriminator_Out=zeros（Simulation_Length1）;
Freq_Control=zeros（Simulation_Length1）;
PLL_Phase_Part=zeros（Simulation_Length1）;
PLL_Freq_Part=zeros（Simulation_Length1）;
%環路處理
C1=0.22013;
C2=0.0024722;
for?i=2:Simulation_Length
Signal_PLL（i）=Signal_Channel（i）*exp（-j*mod（NCO_Phase（i-1）2*pi））;
I_PLL（i）=real（Signal_PLL（i））;
Q_PLL（i）=imag（Signal_PLL（i））;
if?PLL_Mode?==?1
Discriminator_Out（i）=atan2（Q_PLL（i）I_PLL（i））;
else?if?PLL_Mode?==?2
Discriminator_Out（i）=sign（I_PLL（i））*Q_PLL（i）/abs（Signal_PLL（i））;
else
Discriminator_Out（i）=（si