import?cocotb
from?cocotb.triggers?import?RisingEdge


@cocotb.test（skip?=?False）
def?first_test（dut）:
????dut.log.info（“Testing...“）

????COUNT?=?1000
????count?=?0
?
????while?count?????????yield?RisingEdge（dut.clk）
????????count?+=?1

????dut.log.info（“Done!“）

?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????目錄???????????0??2016-05-02?17:28??verilog_ppfifo_demo-master\
?????文件?????????473??2016-05-02?17:28??verilog_ppfifo_demo-master\.gitignore
?????文件????????1067??2016-05-02?17:28??verilog_ppfifo_demo-master\LICENSE
?????目錄???????????0??2016-05-02?17:28??verilog_ppfifo_demo-master\cocotb\
?????文件?????????823??2016-05-02?17:28??verilog_ppfifo_demo-master\cocotb\Makefile
?????文件?????????274??2016-05-02?17:28??verilog_ppfifo_demo-master\cocotb\test_dut.py
?????文件????????1196??2016-05-02?17:28??verilog_ppfifo_demo-master\cocotb\waveforms.gtkw
?????目錄???????????0??2016-05-02?17:28??verilog_ppfifo_demo-master\rtl\
?????文件????????1508??2016-05-02?17:28??verilog_ppfifo_demo-master\rtl\blk_mem.v
?????文件?????????602??2016-05-02?17:28??verilog_ppfifo_demo-master\rtl\cross_clock_enable.v
?????文件???????18905??2016-05-02?17:28??verilog_ppfifo_demo-master\rtl\ppfifo.v
?????文件????????1187??2016-05-02?17:28??verilog_ppfifo_demo-master\rtl\ppfifo_sink.v
?????文件????????1620??2016-05-02?17:28??verilog_ppfifo_demo-master\rtl\ppfifo_source.v
?????目錄???????????0??2016-05-02?17:28??verilog_ppfifo_demo-master\sim\
?????文件????????5202??2016-05-02?17:28??verilog_ppfifo_demo-master\sim\tb_ppfifo.v