?屬性????????????大小?????日期????時(shí)間???名稱
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?????文件???????1401??2007-08-20?14:46??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\alu.v

?????文件???????2287??1999-12-07?15:53??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\basic.rom

?????文件??????15821??2007-08-20?15:00??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\cpu.v

?????文件??????13104??2007-08-20?16:23??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\cpu_test.v

?????文件????????331??2007-08-23?11:16??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\dram.v

?????文件???????1847??2007-08-23?11:18??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\exp.v

?????文件???????4379??2007-08-20?15:08??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\idec.v

?????文件????????460??2007-08-23?11:16??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\pram.v

?????文件???????1523??2007-08-23?11:17??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\regs.v

?????文件???????1765??2007-08-23?11:19??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\risc8.cr.mti

?????文件??????18854??2007-08-23?11:19??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\risc8.mpf

?????文件????1227307??2007-08-20?16:50??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\risc8.vcd

?????文件???????8193??1999-12-08?08:40??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\sindata.hex

?????文件????????338??2007-08-23?11:18??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\transcript

?????文件??????81920??2007-08-20?16:50??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\vsim.wlf

?????文件?????455574??2007-08-20?15:38??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-11.bmp

?????文件?????375786??2007-08-20?15:39??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-13.bmp

?????文件?????278622??2007-08-20?15:39??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-15.bmp

?????文件?????278622??2007-08-20?15:40??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-16.bmp

?????文件?????366222??2007-08-20?15:41??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-17.bmp

?????文件?????411774??2007-08-20?15:42??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-18.bmp

?????文件?????630774??2007-08-20?15:43??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-20.bmp

?????文件?????366222??2007-08-20?15:36??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-6.bmp

?????文件?????366222??2007-08-20?15:36??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-7.bmp

?????文件?????455574??2007-08-20?15:37??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\圖13-9.bmp

?????文件?????443286??2007-08-20?15:35??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\chart\表13-1.bmp

?????文件????1032954??2007-08-20?16:45??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\wave\alu.bmp

?????文件????2709354??2007-08-20?16:38??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\wave\cpu-1.bmp

?????文件????2435454??2007-08-20?16:39??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\wave\cpu-2.bmp

?????文件????1666554??2007-08-20?16:49??Verilog?HDL程序設(shè)計(jì)實(shí)例詳解A\Verilog?HDL程序設(shè)計(jì)實(shí)例詳解?光盤\Chapter-13\risc8\wave\cpu_test.bmp

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