資源簡介
這個分數(shù)有點高了,不過資源絕對讓你滿意,是我自己買了開發(fā)板后送的實驗例程,都是verilog,有些是基礎(chǔ)實驗例程,還有的是電設(shè)的一些賽題,很實用。
代碼片段和文件信息
%???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????
%THIS?IS?A?WIZARD?GENERATED?FILE.?DO?NOT?EDIT?THIS?FILE!????????????????????????????????????????????????????????????????????????????????
%???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????
%---------------------------------------------------------------------------------------------------------??????????????????????????????
%This?is?a?filter?withfixed?coefficients?
%This?Model?Only?Support?Single?Channel?Input?Data.?
%Please?input:??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????
%data?vector:? stimulation(1:n)?????????????????????????????????????????????????????????????????????????????????????????????????
%???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????
%????This?Model?Only?Support?FIR_WIDTH?to?51?Bits
%???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????
%FILTER?PARAMETER???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????
%Input?Data?Type: Signed
%Input?Data?Width: 12
%FIR?Width?(Full?Calculation?Width?Before?Output?Width?Adjust)?:???27
%-----------------------------------------------------------------------------------------------------------
%MegaWizard?Scaled?Coefficient?Values
function??output?=?test_fir_mlab_mat?(stimulation?output)
coef_matrix=[1?1?1?1?1?1?1?0?0?0?0?0?-1?-2?-3?-4?-6?-7?-8?-9?-11?-11?-12?-12?-12?-11?-10?-8?-5?-2?2?7?13?19?26?34?43?51?60?69?78?86?94?102?108?114?119?123?125?127?127?125?123?119?114?108?102?94?86?78?69?60?51?43?34?26?19?13?7?2?-2?-5?-8?-10?-11?-12?-12?-12?-11?-11?-9?-8?-7?-6?-4?-3?-2?-1?0?0?0?0?0?1?1?1?1?1?1?1?];
INTER_FACTOR??=?1;
DECI_FACTOR??=?1;?
MSB_RM??=?0;
MSB_TYPE??=?0;
LSB_RM??=?0;
LSB_TYPE??=?0;
FIR_WIDTH??=?27;
OUT_WIDTH??=?FIR_WIDTH?-?MSB_RM?-?LSB_RM?;
DATA_WIDTH?=?12;
????????????
data_type=?1;
????????%?check?size?of?inputs.
????????[DXDY]?=?size(stimulation);
????????[CXCY]?=?size(coef_matrix);
????????if?(CX?~=?DY?*?INTER_FACTOR)
????????fprintf(‘WARNING?:?coef_matrix?size?and?input?data?size?is?not?match\n‘);
????????end
????????
????????%fill?coef_matrix?to?length?of?data?with?the?latest?coef?set
????????if?(CX?????????????for?i=?CX?+1:DY?*?INTER_FACTOR
????????????????coef_matrix(i:)?=?coef_matrix(CX:);
????????????end
????????end
????????%check?if?input?is?integer
??????? int_sti=round(stimulation);
????T?=?(int_sti?~=?stimulation);
????if?(max(T)~=0)
????????fprintf(‘WARNING?:?Integer?Input?Expected:?Rounding?Fractional?Input?to?Nearest?Integer...\n‘);
????end
????
?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????文件???????7400??2012-09-08?21:27??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\cmm1.vwf
?????文件????????153??2013-06-28?08:35??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\led_test.db_info
?????文件???????1068??2012-09-08?22:03??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\led_test.sim.cvwf
?????文件????????212??2013-06-28?08:35??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\led_test.sld_design_entry.sci
?????文件??????20740??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\led_test_global_asgn_op.abo
?????文件???????2198??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\prev_cmp_led_test.asm.qmsg
?????文件??????24339??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\prev_cmp_led_test.fit.qmsg
?????文件???????8471??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\prev_cmp_led_test.map.qmsg
?????文件??????46043??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\prev_cmp_led_test.qmsg
?????文件???????2352??2012-09-08?22:03??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\prev_cmp_led_test.sim.qmsg
?????文件??????10803??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\prev_cmp_led_test.sta.qmsg
?????文件???????2339??2012-09-08?21:58??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\prev_cmp_led_test.tan.qmsg
?????文件???????8553??2012-09-09?19:45??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\db\wed.wsf
?????文件????????153??2013-06-28?08:35??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.db_info
?????文件???????6179??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.cmp.atm
?????文件?????????33??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.cmp.dfp
?????文件???????2086??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.cmp.hdbx
?????文件????????341??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.cmp.kpt
?????文件??????????4??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.cmp.logdb
?????文件????????228??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.cmp.rcf
?????文件???????3375??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.map.atm
?????文件????????715??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.map.dpi
?????文件???????1762??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.map.hdbx
?????文件???????7995??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\compiled_partitions\led_test.root_partition.map.kpt
?????文件????????653??2010-07-07?17:46??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\incremental_db\README
?????文件???????9511??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\led_test.asm.rpt
?????文件????????310??2010-07-07?17:55??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\led_test.cdf
?????文件?????????26??2012-09-10?16:23??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\led_test.done
?????文件????????239??2012-10-07?10:18??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\led_test.dpf
?????文件?????104688??2012-09-10?16:22??實驗例程(Altera_Verilog)\A-基礎(chǔ)實驗\01-LED顯示實驗\led_test\led_test.fit.rpt
............此處省略2271個文件信息
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