?屬性????????????大小?????日期????時間???名稱
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?????文件?????????14??2005-09-23?01:30??i2c\bench\CVS\Entries

?????文件?????????10??2005-09-23?01:30??i2c\bench\CVS\Repository

?????文件?????????14??2005-09-23?01:30??i2c\bench\CVS\Root

?????目錄??????????0??2006-03-24?09:50??i2c\bench\CVS

?????文件????????200??2005-09-23?01:30??i2c\bench\verilog\CVS\Entries

?????文件?????????18??2005-09-23?01:30??i2c\bench\verilog\CVS\Repository

?????文件?????????14??2005-09-23?01:30??i2c\bench\verilog\CVS\Root

?????目錄??????????0??2006-03-24?09:50??i2c\bench\verilog\CVS

?????文件??????11433??2005-11-10?17:53??i2c\bench\verilog\i2c_slave_model.v

?????文件??????11433??2005-11-10?17:53??i2c\bench\verilog\i2c_slave_model.v.bak

?????文件???????3948??2005-11-10?18:09??i2c\bench\verilog\spi_slave_model.v

?????文件???????3949??2005-11-10?17:42??i2c\bench\verilog\spi_slave_model.v.bak

?????文件??????14443??2005-11-10?17:40??i2c\bench\verilog\tst_bench_top.v

?????文件??????14443??2005-11-10?17:40??i2c\bench\verilog\tst_bench_top.v.bak

?????文件???????5581??2005-11-10?17:51??i2c\bench\verilog\wb_master_model.v

?????文件???????5581??2005-11-10?17:51??i2c\bench\verilog\wb_master_model.v.bak

?????目錄??????????0??2006-03-24?09:50??i2c\bench\verilog

?????目錄??????????0??2006-03-24?09:50??i2c\bench

?????文件????????102??2005-09-23?01:30??i2c\CVS\Entries

?????文件??????????4??2005-09-23?01:30??i2c\CVS\Repository

?????文件?????????14??2005-09-23?01:30??i2c\CVS\Root

?????目錄??????????0??2006-03-24?09:50??i2c\CVS

?????文件?????????59??2005-09-23?01:30??i2c\doc\CVS\Entries

?????文件??????????8??2005-09-23?01:30??i2c\doc\CVS\Repository

?????文件?????????14??2005-09-23?01:30??i2c\doc\CVS\Root

?????目錄??????????0??2006-03-24?09:50??i2c\doc\CVS

?????文件?????211471??2003-07-03?23:20??i2c\doc\i2c_specs.pdf

?????文件?????????51??2005-09-23?01:30??i2c\doc\src\CVS\Entries

?????文件?????????12??2005-09-23?01:30??i2c\doc\src\CVS\Repository

?????文件?????????14??2005-09-23?01:30??i2c\doc\src\CVS\Root

............此處省略193個文件信息